This application claims the priority benefit of Taiwan application serial no. 90122075, filed Sep. 6, 2001.
1. Field of the Invention
The invention relates to an ESD protection circuit. More particularly, the invention provides an ESD protection circuit which robustness is improved.
2. Description of the Related Art
Electrostatic discharge (ESD), depending on ambient conditions including various parameters such as humidity rate, may occur whenever during the fabrication process of an integrated circuit (IC) chip or after the IC chip is achieved. When it occurs, the electrostatic discharge can irreversibly damage a part of the IC chip. To prevent ESD damages, ESD protection circuits are therefore conventionally coupled with the IC chips.
Referring to FIG. 1, a circuit diagram schematically shows an example of a conventional ESD protection circuit. As illustrated in FIG. 1, a conventional ESD protection circuit may comprise a NMOS transistor 102 and a PMOS transistor 110. The NMOS transistor 102 has its drain connected to, for example, a power supply voltage VDD, its source connected to a substrate biasing voltage VSS that can be, for example, a ground potential, and its gate connected to an input pad 112. In turn, the PMOS transistor 110 has its drain and source respectively connected to the power supply voltage VDD and the input pad 112 while its gate is connected to the power supply voltage VDD.
Furthermore, an input buffer comprising a NMOS transistor 106 and a PMOS transistor 104 is typically provided between the above ESD protection circuit and an IC chip 108.
When no electrostatic discharge occurs, both NMOS transistor 102 and PMOS transistor 110 are switched-off, and no current passes through the ESD protection circuit. The normal operation of the IC chip 108 is therefore not affected.
When an electrostatic discharge occurs, it results in an increase of the drain voltage of the NMOS transistor 102. Depending on the polarity of the electrostatic discharge, the increase of the drain voltage caused by the electrostatic discharge may exceed the breakdown voltage of either the NMOS transistor 102 or PMOS transistor 110. A resulting junction breakdown between the drain and the base (the base is typically a p-substrate (or p-well) in NMOS transistor and a n-well in PMOS transistor) triggers on the parasitic BJT, which then generates a current flow through either the NMOS transistor 102 or PMOS transistor 110. Extreme electrostatic charge can be therefore bypassed through either the NMOS transistor 102 or PMOS transistor 110, protecting thereby the IC chip 108.
As semiconductor processes emphasize on the manufacture of thinner gate oxide, the level of the gate oxide breakdown voltage is accordingly lowered. As a result, if the gate oxide breakdown voltages of the NMOS transistor 106 and PMOS transistor 104 are critically close to those junctions of the NMOS transistor 102 and PMOS transistor 110, electrostatic discharge may directly pass through and damage the gate oxide of the input buffer.
Referring to FIG. 2, a circuit diagram schematically shows a conventional gate-coupled ESD protection circuit. As illustrated in FIG. 2, the conventional ESD protection circuit comprises two NMOS transistors 202, 206. Specifically, the ESD discharge NMOS transistor 202 has its drain connected to the power supply voltage VDD, its source and its base connected to the ground, while a parasitic capacitor 204 further connects from the gate to the drain thereof. The gate of the NMOS transistor 202 further connects to both the gate and the drain of the NMOS transistor 206. Meanwhile, the source and the base of the NMOS transistor 206 are connected to the ground.
When an electrostatic discharge event occurs, the arrangement of the parasitic capacitor 204 and the NMOS transistor 206 generates a voltage at the gate of the discharge NMOS transistor 202 that can reduce its avalanche breakdown voltage, which may solve the problem of the ESD protection circuit of FIG. 1.
In connection with the behavior of the above ESD protection circuits, FIG. 3 is a graph that typically plots the relationship between the ESD voltage and the ESD current of respectively a gate-grounded and gate-coupled ESD protection circuit. In FIG. 3, curves 302, 302xe2x80x2 plot the variation of the ESD current with respect to the ESD voltage for a gate-grounded ESD protection circuit (circuit illustrated in FIG. 1). Curve 304 illustrates the variation of the ESD current with respect to the ESD voltage for a gate-coupled protection circuit (circuit illustrated in FIG. 2).
As illustrated in FIG. 3, when an electrostatic discharge event occurs, the avalanche breakdown voltage of the gate-grounded ESD protection circuit is approximately 15V while the ESD current that can be sustained does not exceed 0.8A. In contrast, the avalanche breakdown voltage of the gate-coupled ESD protection circuit is lower, being approximately 9.5V while the ESD current that can be sustained is above 1A. The robustness of the gate-coupled ESD protection circuit is therefore relatively higher than that of the gate-grounded ESD protection circuit.
Referring to FIG. 4, a circuit diagram schematically shows another conventional ESD protection circuit, which is a gate-driven ESD protection circuit. As shown in FIG. 4, a conventional gate-driven ESD protection circuit may comprise an ESD discharge NMOS transistor 402 that has its gate connected to a Zener diode 404 and a resistor 406. The Zener diode 404 connects from the gate of the ESD discharge transistor 402 to the power supply voltage VDD while the resistor 406 connects from the gate of the ESD discharge transistor 402 to the ground.
When an electrostatic discharge occurs, it generates a reverse breakdown of the Zener diode 404, which creates a current flow through the resistor 406. The gate voltage of the discharge NMOS transistor 402 is therefore greater than the threshold voltage of 0V, which decreases its avalanche breakdown voltage. Gate-driven ESD protection circuits and gate-coupled ESD protection circuits therefore have the same characteristics of lower avalanche breakdown voltage and better robustness.
Referring to FIG. 5, a graph schematically plots the relationship between a human-body model (HBM) ESD voltage and the gate bias of an ESD discharge transistor for a fixed channel length L of 0.8 xcexcm and various channel widths W. In the graph, the level of the human-body model ESD voltage depicts the robustness of the ESD discharge transistor. With respect to an ESD discharge transistor having, for example, a channel width W of 600 xcexcm, if the gate bias is 0V when the electrostatic discharge event occurs, the ESD robustness of the discharge transistor is about 2.2 kV. If the gate bias is within a range of about 3V through 8V, the ESD robustness of the ESD discharge transistor increases to a constant level of about 3.8 kV. If the gate bias increases over 9V, the ESD robustness of the ESD discharge transistor rapidly decreases.
In the conventional protection circuits illustrated in FIG. 2 and FIG. 4, the gate bias of the discharge NMOS transistors 202, 402 is substantially depending on the electrostatic discharge that contacts with the power terminal VDD and the ground terminal. With respect to high levels of ESD stress, the gate bias is consequently increased, which results in an ESD robustness that is disadvantageously lowered. The conventional gate-driven ESD protection circuit may be therefore ineffective in this context.
An aspect of the present invention is to provide a gate-coupled or gate-driven ESD protection circuit that can discharge excessive electrostatic charge with an improved ESD robustness thereby effectively protecting a principal circuit.
To accomplish the above and other objectives, the invention provides an ESD protection circuit that is connected between two potential terminals of a principal circuit to discharge electrostatic current. The ESD protection circuit, according to an inventive concept of the invention, is arranged between a first and second potential terminal of the principal circuit, and comprises a RC branch, a voltage adjuster circuit, and an ESD discharge transistor. The RC branch includes a resistor and a capacitor that are series connected from the first potential terminal to the second potential terminal, wherein the resistor connects the capacitor via a connection node. The voltage adjuster circuit has a first input port connected to the first potential terminal, a second input port connected to the second potential terminal, and a third input connected to the connection node between the resistor and the capacitor of the RC branch. The voltage adjuster circuit further has an output that is connected to the gate of the ESD discharge transistor. The drain and the source of the ESD discharge transistor are respectively connected to the first and second potential terminal to discharge excessive electrostatic charge. In normal operating conditions of the principal circuit without occurring an electrostatic discharge even, the voltage adjuster circuit does not conduct current and the output coupled with the gate of the ESD discharge transistor turns off the ESD discharge transistor. By coupling the third input of the voltage adjuster circuit with the RC branch, the voltage adjuster circuit reacts with the occurrence of an electrostatic discharge pulse. If an electrostatic discharge pulse contacts with the first or second potential terminal, the voltage adjuster circuit accordingly becomes current conductor, and the output thereof adjusts the gate voltage of the ESD discharge transistor to obtain an uniform turn on of the ESD protection circuit for bypassing ESD current. The gate voltage of the ESD discharge transistor is adjusted to an optimal value to further obtain an optimal ESD robustness of the ESD discharge transistor. By controlling the gate bias of the ESD discharge transistor, the gate oxide thereof is not damaged when an electrostatic discharge event occurs and the turn-on speed of the ESD discharge transistor is improved.
The voltage adjuster circuit of the invention may be variously implemented. The voltage adjuster circuit principally comprises a plurality of MOS transistors that are electrically arranged with a common gate connection and a chain connection of their sources/drains from the first potential terminal to the second potential terminal. To improve the voltage adjustment of the voltage adjuster circuit, various additional voltage clamps such as diodes may be arranged in the chain connection between the first and second potential terminal and/or between the output of the voltage adjuster circuit and the second potential terminal. By using MOS transistors in the voltage adjuster circuit, the gate voltage of the ESD discharge transistor can be properly adjusted with respect to high levels of ESD stress.
According to another inventive concept of the invention, the ESD protection circuit may comprises a RC branch, a plurality of voltage adjuster circuits, and a plurality of ESD discharge transistors. The RC branch includes a resistor and a capacitor that are series connected from the first potential terminal to the second potential terminal, wherein the capacitor connects the resistor via a first connection node. The drain and the source of each ESD discharge transistor are respectively connected to the first potential terminal and the second potential terminal to discharge electrostatic charge. Each voltage adjuster circuit has a first input port connected to the first potential terminal, a second input port connected to the second potential terminal, a third input, and an output. The output of each voltage adjuster circuit is connected to the gate of one ESD discharge transistor. The voltage adjuster circuits are connected to one another via connecting the third input of one voltage adjuster circuit to the output of another voltage adjuster circuit, wherein the third input of one of the voltage adjuster circuits is further connected to the first connection node. With the above ESD protection circuit, uniform turn on and optimal ESD robustness of the ESD discharge transistors can be accomplished to effectively bypass electrostatic charge.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.